New memory boards for the P2

  • Hello!

    In late November I bought my second P2 unit, an Italian one. Before it arrived, I started thinking about spare parts and how expensive and difficult to find are some of its components. So I started a project to replace any faulty memory board on any P1/P2. I called it "Elephant", as elephants have good memory. The goal is to produce new boards with new and lesser ICs (all of them modern, of course). At this point I have two designs: a minimalistic 3-ic design which provides 48KB called "pygmy" and the complete, switch-configurable to 32, 48 and 64Kb with 10 ics called "mammooth".

    Yesterday I finished soldering all wires on the "pygmy" prototype and tested it on the Italian unit. the full 48Kb memory was recognized and I could boot to CP/M with no problem at all. I am currently rewiring the prototype to turn it into an 8-ic 64Kb board.

    The wire-wrapped board, front side.

    The wire-wrapped board, back side.

    The prototype board attached into the bus.

    The prototype board, during testing. 4010-FFEF message returned after cold reset.

    Here are the schematics for the "pygmy", which is the one tested. I'll post the next version once I have tested it.

    Once the second and final version is tested, I'm planning to design the board itself and place an order to manufacture them. I hope helps to extend the life of these computers a few more years.

    Thank you very much!

  • Welcome here! You did a very nice job!

    Thank you. :)

    I won't kept my word so I'm posting the first version of "Mammooth" schematics before its testing. It should be able to address 64K by writing at the register at 0x78. Two of the ICs are to protect the computer, my first aproaches with the switch was to drive directly the decode signal through them, but I realized that if someone accidentally modifies the switch with the computer powered and working there could be some problems, so I decided to put an extra '74 to store the position of the switch when it powers up. I'm wiring the prototype without this protective section, but if this design gives you enough confidence I could give up on that scary wire-wrap and order a batch for testing.

    P2 - Mammoth.pdf

    What do you think about it?

  • Hello Jaume,

    I am pleased that you have again written a great contribution to the TA alphatronic Px systems in the Germany FORUM.

    I'll get straight to the new extension (memory switch) of a memory card.

    I mean, it's not necessary to switch to a memory size of just 32 kB for a P1.

    switch-configurable to 32, 48 and 64Kb

    I actually had never found a P1 then and never did.

    So the new card should behave exactly like the HARD-RESET or POWER ON on 4000h to FFFFh as 48 kB.

    This will initially start a P1 (if available) and a P2 and work fine!

    Also always starts a P2S, P2U, P3, P30 with the 48 kB memory.

    Now it should be possible to make a BANKING via the PORT 78h.

    Just like you will make it sure.

    In the cp /m for 64kB versions there are each switched to 64kb (0000h to FFFFh) or there in the MOS routines on again 48kB memory with access to the MOS 0000h to 1BFFh or from 3000h to 3FFFh in the VIDEO memory.

    I hope the suggestions are helpful.



  • Hello Helmut, glad to see you here!

    In the 64K version of the board, the lower 16K are switched on/off by writing x1xxxxxx/x0xxxxxx at 78h (wired as 87h as the bus is negated). The switches only "cut" functionality of the circuit to ignore banking or decode logic. The lower 16K are disabled when reseted (or powered on) and can only be enabled by writing into the register if the switch allows it to.

    Apparently there are at least a pair of P1 units running free on the wild, excluding them is not an option for me. Sooner or later they will appear and require some help.

    I don't know how would this work with a computer other than the P1/P2 models. As the P1 is a cut-down version of the P2 is easy to see how to proceed, but the P3/P4/P30/P40 models are improved versions and unfortunately I have no units of these models to test any of my designs. However, if this can solve issues for all the range of the computers I'll be happier than if it only solves issues for the P2.

    The schematic previously posted is a preview, so it is unfinished and it may contain errors and need a pin rearrangement for the RAMs. Don't use it yet, please.

    Thank you very much!

  • Greetings!

    Today I've finished wiring the 64K wire-wrapped prototype. Although I soldered the switch I left it non-functional as I saw it was simpler.

    However, the wire-wrap is a mess and I got lost between wires. At the end, I performed a test and this is all I could get.

    The memory was not recognized by the computer, so obviously something was wrong in that board. I think the problem was not design, as it is very simple. The main issue there is the amount of wires between both memories and the connector. It's hard to work at that area of the board, it is crowded. Although this test was a failure, I will continue development of the board, probably developing a more serious solution other than wire-wrap.

  • Hi jlopez,

    awesome project :thumbup:

    I don't know how would this work with a computer other than the P1/P2 models. As the P1 is a cut-down version of the P2 is easy to see how to proceed, but the P3/P4/P30/P40 models are improved versions and unfortunately I have no units of these models to test any of my designs. However, if this can solve issues for all the range of the computers I'll be happier than if it only solves issues for the P2.

    I'm using both P2U and P30. My P2U has an single 64K Memory card, which also works with the P30 and vice versa. Therefor, if you do it right, your "Mammoth" should work together with P3, P30, P4, P40 too. Like helwie44 already wrote: All this Px machines starts in 48K mode.

    In order to make it easier for you, I agree with @Helwi44 that a 32K mode isn't necessary, because every P1 should also work with 48K and their owners will be very happy about the upgrade.

    I'll follow your reports with great interest.

    Best regards


  • Greetings!

    I'm preparing a small prototype batch. Wire-wrap was most probably the cause of failure and cutting thin tracks and soldering only a few wires is better than that monster. It's the right time to make a few corrections and additions. I'm doing the firs part (corrections), however you are not the first to state that it may work with improved models of the computer family. What the requirements for the P3/30/4/40 are (memory map, io ports, values to make it switch, etc.)?

    About the 32Kmode, it does not complicate it, I know were to cut the line. It may not be necessary and I doubt it will be ever used. However, I prefer giving the user the chance of choice. It's just like the ZX-81, it can have up to 32K internal ram, 16 internal or external or just the 1K or 2K of the original build. There are people who upgrade and people who doesn't. The ones who doesn't don't want because they want to be in touch with the original limitations the original computer specs had. Nostalgia is very a curious feeling... :)

  • I've checked the specs and seems that from the P2 onwards all computers on this family have only 64K... The memory map seems the same... So the P3/P4 are only P2U with different case, detachable keyboard and better floppy drives/hard drive? It's strange that no memory upgrades were made. Also I heard that the P30/40 are P3/P4 with an extra 8088 card... Sounds interesting.

  • Exactly - TA had a 64 kB memory card for the P2 and P3 and P4 series.

    This made it easier with a TA 64/48 KB memory card more economical.

    Thus, a 48 kB memory was always available with the MOS after the RESET or POWER ON.

    Internally with the cp / m over PORT 78H there is switched to 64 kB and / or again to MOS access as needed.

    The P30 .. P40 series was simply a 8086 card with a ribbon cable to its own RAM of 128 ... 512 kB. So there is an MSDO 2.0. The IOs from the MSDOS are handled via an interfache program (paralle PORT) to the 8085 on / from the hardware components (DISPLAY, KEYBOARD, FLOPPY +++).

    Here in the FORUM are many contributions in the range "Triumph Adler" to the TA P3, P30 available.

  • Hello,

    This morning I've read about the 128K expansion on the P30/40 computers. Is this memory "seen" by the 8085? If it is, wouldn't you know what port should I access? I assume that the backplane pinout for columns A and B doesn't differ when comparing P1/2-P3/4 models, but is worth asking if it does before sending the gerber to some manufacturer.

    Max. in two days I'll put this project to a short sleep. This semester is reaching its end and I still have work to do (I've to hand-copy lots of kanji!). When the work is done, I'll wait for the prototype PCBs to arrive (I'll try to order them before switching back to Japanese mode).

    Thank you very much!

  • Hello Jaume,

    More infos with this LINK P30cards. for TA P30 machine.

    The 16-bit processor is fed via a ribbon cable to the extra-memory (128 kB..).

    The motherboard uses only IO and control signals and voltages from the 96 VGL.

    The picture shows the principle - I hope.

    Otherwise I have no circuit information. Possible in the FORUM but still some PHOTOs other construction maps.

    Die Karten in slots 2, 4 und 5 sind über ein Flachbandkabel miteinander verbunden (angedeutet durch den blauen Balken am rechten
    Rand der Liste).

    Good luck with the languages - and soon with the memory card again.



  • Simple static memory expansion for KISS - or TA P2x?

    Here I have a KISS memory card with 48 kB static RAM chips. About a friend of that time I got this card - for my KISS (Prototype as a further development to the TA P2x systems).

    The works error-free, which could actually work properly in an alphaTronic P2U possible - I'll test it later).

    48 kB Range fix 4000h - 0FFFFh

    Unfortunately, I have no schematics. For this I have made very good PHOTOS.

    Detail - chip's.


    The 16kB switching 16Kb RAM to see this later.

  • Wow, that's a nice board!

    There aren't schematics but I think I have a vague idea of how it works.

    There are three bus transceivers. Two of them are '373 and the other one is a '245. I don't see anybody working with half address bus in positive logic and the other half in negative (it could be, but I don't see it) so let's assume he negated the full address bus to operate the memories with positive addresses and left the data negated.

    I imagine the '00 is wired in a similar way as my '02 and the result is fed to the '138 enable pin. The more RAM ICs on a circuit, more complex is to drive them, so the '138 was most probably added to the design for this reason. The select pins may be fed by A15, A14 and A13.

    The only thing that I cannot figure why was done is that 8 DIL switch and a '30 (that is a 8-input NAND gate)...

    Note that this analysis is made after a quick look at the board, don't know if it actually works this way, but that's how imagine it working. May be wrong. :S

  • KISS 16 kB static RAM board

    Here I show this card, which is arranged from 0000 to 3FFFh. But after RESET or exactly as with the TA alphaTronic P2U can be switched by PORT 78h! Unfortunately I do not have a wiring diagram.

    16 kB RAM - banking 0000 to 3FFFh

    I mean there is a tricky building block on the card. The TPS 28 S 42 N is a PROM?

    For this I have a data sheet possibly the TMS chip on since 4-16 (PDF) corresponds.

    But I have no thoughts at the moment about the possible circuit works (theoretically !!).

    However, both RAM cards (the 48kB and also this 16kB in a sks KISS machine) really work.

    I think - manipulating with a PROM for the addresses is probably tricky - right?

    Tomorrow I test both cards in my TA P2U.

  • After a cup of coffee I quickly put the static cards in you TA P2U:

    Everything went just like the 64 kB memory cards.

    TA alphatTronic P2U - with static RAM-cards.

    Boot from GOTEC (drive A:) with 64 kB - cp/m banking.

    My TA P2U with A: GOTEK, B: PANASONIC 2 head drive, and with a parallel interface to the 5 MB SyQuest (Q-PACK removable cassettes) work very well.

    Last FOTO run from 5 MB SyQUEST under cp/m 63k Version.

    A part from cmd XDIR.COM - pagestop if more 80-files!Veri

    Very nice.

  • Greetings!

    I'm here again. I'll resume my work on this for a few days, but I'll need to be gone again some days before the exam... Still I think there's time enough to start redrawing the third iteration of the board. The second prototype of "mammooth" still needs to be ordered because as it was the first time and I didn't knew if I had enough time before the deadlines I prefered to do it after those events.

  • Hello Jaume,

    Thanks for the message about the new P2 memory card.

    I hope I do not cause any uncertainty as the board should be optimally designed?

    As background information I have the circuit diagram of the DS 2069 memory card terminal of the company Dr.-Ing. R. HELL, Kiel added.

    I have again the schematic of DS 2069 sentence terminal of the company Dr. - Ing. R. HELL, Kiel

    For this I add the 128 kB board. It is actually compatible with the MC80-BUS (sks, TA and HELL).

    But in the case of the 96-pin connectors, the C- connector series often has small deviations.

    The BANKING on the 128 kB HELL card is also developed via PORT 060h.

    Do you have joy and much success.

  • Hello Helmut,

    Thank you for the schematics!

    As you know, I have hand-drawn a few ideas, and these days I'll try to find a state of harmony between them and the existing schematics. I don't plan to have a 128K board yet. However I won't stick to 64K. The third iteration will be a 66+6K (or 65+6K, I'll need to do some more research about). As 8 ICs per 18x10 cm is wasting the board, I'll focus to integrate a 6116 2K SRAM and a 2764 pin-compatible ROM. Most decode logic is already there, a few additions should be made to address those. However placing a ROM generates a new problem, as this component cares if their addresses or data are negated.

    The placement of the ROM came bacause I found that (as I already stated) most decode logic was already present and making a System ROM replacement board was a bad idea, as decode logic would be duplicate within the memory board and still it would have a low IC count. Considering both ideas brought me to modify the current board into a complete RAM-ROM replacement.