Troubleshooting TA P2 48K RAM Board

  • Hallo Leute :)


    Sorry I didn't have time to follow up on this problem. It was a long story with a even longer delivery for a spare 8202A, I got a wrong chip, then a new one was delivered and out of dispair I finally changed all the control chips in the CAAC09 to get to the same results. :stupid:

    Thanks a lot for all the insights and leads you threw into this topic, specially to helwie44, gpospi and jlopez. Really appreciated.:)


    I had some time to take a look to it again. I came to the following findings/conclusions thay may be right or wrong :)


    - There is a connection in the backplane between the 48K and the 16K boards. My theory is that it allows to disable PCS from the 16K card. This makes probably sense because the output buffers of the 16K board are always active (the 74LS240 has the output enable line to GND) and therefore there must be a way to avoid both output buffers in both cards to be enabled at once. This is performed by the backplane connection on pin 75 or at least this is what I have observed in my setup.


    - jlopez is right regarding PCS and RD/WR signals on the 8202. In order to start a read/write cycle and eventually get XACK, what is also needed to turn on the output buffers (i8083) of the 48K CAAC09 card, PCS must be active (low) and a read or write operation should have been initiated.


    So I'm now in the situation where after replacing all the control chips on the CAAC09 card and testing that I get XACK and activation of the output buffers consistently when I try to read from MOS the memory in the $4000-$40FF zone, I'm still seeing the known pattern of memory reads where the data value matches the lower address bits. At the same time, accesses to the 16K dynamic card (CAAC08) are working properly, both read and write requests.


    This makes me think the problem is not in the RAM card itself but in some logic in the CPU card CAAA06. My guess is that something goes wrong when the RAM is selected, but only for the RAM in the $4000-$BFFF area. This can be somehow related with the banking mechanism too.

    I was not able to find any schematics of the CPU cards, therefore I guess I would have to reverse engineering the connections to pinpoint how the RAM selection works exactly, what chips are involved and how/when the data in the backplane data bus is brought into the CPU bus.


    Another fact that leverages this theory is that there is no easy way the 48K card can provide the lower address bus content in its data output buffer. The buffer inputs (i8083) are connected directly to the output pins of the 4116 RAM chips and I've checked that they got enabled on a read request, therefore seems pretty probable that the problem is in the CPU board itself. What we would expect on a faulty RAM is random or improper values in the data bus, but not the lower address bus content mirrored. This only makes some sense in the CPU board content, where the lower address bus/data bus are multiplexed on the same lines.


    Saludos

  • Thank you overCLK ;

    for your detailed interim report.

    I'll take a closer look at your content of the information later.


    BANKING:

    For a few days I have been thinking about how I or a P2U USER from FORUM (banking 48/64 kB) could precisely identify the components (plug-in cards and possibly switching details) using measurement technology - such as Scope or a multi-channel analyzer.


    Which plug-in cards exactly and how?

    Basically, the following cards are possible involved :?

    • Memory card /?
    • CPU card!
    • Display card?

    To compare I have a sks / CPU card - which has some hardware changes (patch wire) and only a piggyback chip on the CPU. This should run in a P2U exactly like the TA-P2U operated with 4300h and 0100h cp / m.

    I will try to document this sks-modified CPU precisely and make it available. But at the moment it still takes some time ...


    Oh yes - unfortunately I hadn't saved any circuit diagrams of the KISS / or the TA P2U plug-in cards!

  • Greetings

    - There is a connection in the backplane between the 48K and the 16K boards. My theory is that it allows to disable PCS from the 16K card. This makes probably sense because the output buffers of the 16K board are always active (the 74LS240 has the output enable line to GND) and therefore there must be a way to avoid both output buffers in both cards to be enabled at once. This is performed by the backplane connection on pin 75 or at least this is what I have observed in my setup.


    I found the scan of the paper I made long ago regarding CAAC08. Sorry, it's not the cleanest but I hope it gives some insight of how this works.


    In case you need schematics for the CPU board, I don't have them but I have the next best thing: the scans of the bare, unpopulated board on which to perform the reverse-engineering process. Reference is CAAA08 (P3) so there may be some differences such as a single 4k ROM, etc.

    When I tried to list all retro systems I have at home, the "The message is too long, must be under 500 characters" error appears! :lol:

  • Greetings

    In case you need schematics for the CPU board, I don't have them but I have the next best thing: the scans of the bare, unpopulated board on which to perform the reverse-engineering process. Reference is CAAA08 (P3) so there may be some differences such as a single 4k ROM, etc.

    Hey jlopez

    that would probably help. Thanks a lot. I have spent some good hours trying to figure out all the logic to enable the bus transceiver in the CPU board, but some tracks are quite difficult to follow. Probably the scans would help in case they use more or less the same chips, what I expect.


    So far I was not able to pinpoint any clear bad behavior with the signals:


    During the read cycle on $4000 zone, RD and XACK are measured on the 8202 and T and OE are the control signals to the 8287 bus transceiver in the CPU board.

    T makes sense to me, setting the direction towards the CPU bus, but OE seems to last too long. Anyways, since T is controlling the direction, doesn't seem a problem by itself I guess since T only allows data towards CPU before XACK is disabled. The output buffer of the memory card follows the same timing as XACK and so during XACK low the data should be consistent in the backplane.

    Of course there could be many other problems related, like the transceiver being defective and not enabled (but that would also affect the extra 16K card in $C000 and that is working fine).

    I would need to measure the same while reading on $C000 with the 16K card in.

  • Thanks helwie44 for your analysis.

    But I'm afraid you're right. Nearly anything can produce a problem like this one. What I think are good hints in my case:

    - The 48K card seems to work OK, control signals wise. Even if I remove one of the RAM chips, the result is the same. Since I changed all the logic chips and even tried with another 8283 output buffer, I started to think the problem may be in a different place

    - I'm able to read and write data to the 16K card. This means that the transceiver in the CPU card is able to do its job, but for some reason something goes wrong with the 48K card.


    I was wondering if it's possible to change the banking from MOS with some command. Checked the manual but was not able to figure out if it's possible to send an OUT to the CPU to modify the banking mode. Do you know if this is possible?


    It's a pity that the schematics are no longer available. :cry2:

  • I was wondering if it's possible to change the banking from MOS with some command. Checked the manual but was not able to figure out if it's possible to send an OUT to the CPU to modify the banking mode. Do you know if this is possible?


    It's a pity that the schematics are no longer available. :cry2:

    It would be out 0x78, 0x20 // out 0x78,0x60; you could trigger it using the system hex monitor. However, if the test program is not well-written you may lose MOS control and become stuck in the extended bank until reset.


    Yeah, that's sad; but let's not cry over spilled milk, do we? After all it is how war is, and time is an unforgiving enemy. Fortunately, even if we (P2/P3 users) are a small community inside this generation of computers' curators we may succed in preserveng them with the help of one or another. Fortunately helwie44 has been able to save most of the software related documents, so the soul of the system is mostly safe.


    Returning to more practical matters, I could post the scans here or alternatively I could upload them to a new git repository so anybody interested could work on it. What do you prefer?

    When I tried to list all retro systems I have at home, the "The message is too long, must be under 500 characters" error appears! :lol:

  • Hello jlopez and overCLK -

    thanks for your onsiderations.

    I was wondering if it's possible to change the banking from MOS with some command. Checked the manual but was not able to figure out if it's possible to send an OUT to the CPU to modify the banking mode. Do you know if this is possible?

    From my practical experience it is possible with one OUT command - but only from the MEMORY greater than 4000h is executed by the CPU to switch the memory RAM and / or the display.

    This means that the address area of the CPU card must be switchable from 0h to 3FFF. With that included, it might just be possible somehow:

    • MOS range 0h-17FFh and
    • RAM-MOS 1800h to 1BFFh and possible the whole (possibly a side effect) ??
    • DISPLAY RAM? 2000h to 3FFF

    to switch.


    Returning to more practical matters, I could post the scans here or alternatively I could upload them to a new git repository so anybody interested could work on it. What do you prefer?

    YES jlopez , your comments are exactly my opinion. We should invent a new THREAD to decipher some basics - for all users.


    At that time I had developed some software emulations in the GIT system with rfka01, such as the ITT3030, alphaTronic P30, P3, P2U, P1.

    The equipment was provided by a large number of developers. But I had mostly sent a lot of internal technical information via rfka01 and he built this data into the GIT.


    Would a GIT project then be a hardware problem?


    Greetings @ hellwie44


  • Well, by small I meant we aren't like the Commodore or Spectrum user groups and as such we must rely more on ourselves.

    I suggested GIT because it provides a high degree of reliability regarding the members and how they manage the project. In case of the foresaid board, I retraced around half the tracks but every time I tried to continue I lost focus and had to stop. While github is mostly software-oriented, there are also hardware projects dwelling around.



    Don't worry about that. I could teach you how to do it, but only if you are ok whith it ;)

    When I tried to list all retro systems I have at home, the "The message is too long, must be under 500 characters" error appears! :lol:

  • If structured correctly we could store all related datasheets, lists of compatible references for the main ICs, manuals, system ROMs, schematics (with US logic nomenclature), kicad symbols and footprints for obsolete parts.

    When I tried to list all retro systems I have at home, the "The message is too long, must be under 500 characters" error appears! :lol:

  • Repository created.


    SKS-Alphatronic-DS Archive


    It actually contains some of the datasheets related to the main ICs of the computer, the Spanish Char ROM and the scans for CAAA08. I suppose I could add more data yet today it's not the best to dig into my hard drive. Still, it is accessible for in case anybody wants to add/modify anything.


    Best regards

    When I tried to list all retro systems I have at home, the "The message is too long, must be under 500 characters" error appears! :lol:

  • First, you need to clone the repo. This means creating a local copy of it into your computer.


    The easiest way is by selecting "Code>Open With gitHub Desktop"



    Then a folder structure will be created on your hard drive. Github Desktop will take account of the changes you make and, when you are sure the contributions you made are fine enough then using GitHub Desktop you shall proceed to commit and push.



    Summary is mandatory, description is recommendable. After that you may see push on that same screen; that would add the changes into the repository.


    Regards

    When I tried to list all retro systems I have at home, the "The message is too long, must be under 500 characters" error appears! :lol:

  • Very nice jlopez. I was able to superimpose both sides with layers on Gimp and now following a trace is a piece of cake. :-)

    I just need to go enabling the proper side of the board when I reach a via, what is very time consuming and sometimes quite tricky with just the populated board:



    Thanks a lot. :)

  • Don't worry. Tomorrow I'll prepare some crash course for you.

    When I tried to list all retro systems I have at home, the "The message is too long, must be under 500 characters" error appears! :lol:

  • No need to thank. In reality, I should thank you. I tried to map it two or three times, but my head is not where it should be. At least for me its a relief you find it useful. You may need the component layout too to trace it correctly, tomorrow I'll scan it.

    When I tried to list all retro systems I have at home, the "The message is too long, must be under 500 characters" error appears! :lol:

  • Don't ask me what happened exactly but... die Alphatronic ist wieder da :shock:


    I focused again in the 8283 latch that connects the memory to the backplane data bus. connected the analyzer to the input and output for D0 and also to the STB and OE signals on the chip. It was clear that when the memory output was zeroed, the output of the latch with STB and OE enabled was not one (the 8283 has negated outputs).

    What is weird and funny is that I already tried with a replacement for this chip days ago, but I tried again, and this time, the Reset message took a while to dissapear giving me finally a RAM TOP at BFFF (the 16K card was not inserted).

    16K card in again and here we are:




    To be honest, I'm not completely sure if the old 8283 was really broken or there is some bad contact in the board. Let's see if it keeps working but finally it seems the problem was in the memory board itself.


    Nice to have it working again. Thank you all for your kind support :-)

  • Your screenshot made me notice another interesting fact regarding different versions of P2.

    My P2 (even the late one with the 48 KB DRAM card) has 3 EPROMs on the CPU card and starts with the following screen:

    The start message of my P3 (with 64 KB) is actually much closer to your screen (notice "RESET" vs. "Reset", "MOS-3" vs. "CAAP" and top of memory "FFEF" vs. "FFFF"):

    This might be a further indicator that 64 KB P2 systems indeed require a different CPU card (and EPROM version), unless there are certain "hacks" as obviously done for @helwie44's system. I think there have been some postings showing P2 CPU cards with only two EPROMs (just as on P3 CPU cards), is this also the case in your system?


  • Genau! :-)

  • Hallo overCLK :

    Wie fast von Geisterhand - Gückwunsch und gut das die Maschine nun arbeitet.

    Don't ask me what happened exactly but... die Alphatronic ist wieder da

    But with the contact problems with various plug connections, the error could have occurred at first.

    You're going to check everything several times later.


    Greetings and have fun with your machine.

    helwie44

  • Hallo P2 Fans,


    in diesem Thread wurde ja schon einiges über die Speicherorganisation und das Bankswitching der P2 Rechner von SKS / TA erfolgreich erforscht. Vorgestern bin ich über die hier angehängte Beschreibung der dynamischen 16K RAM Baugruppe CAAC08 gestolpert, die vermutlich auch die noch verbliebenen Fragen zu dem Thema größtenteils beantworten dürfte. Die 16K RAM auf der Karte dienen als Common Bereich (Adresse C000H - FFFFH), der nicht ausgeblendet werden kann. Diese 16K können aber nur verwendet werden, wenn sie vom Controler 8202 einer ebenfalls im System vorhandenen 48K RAM Karte angesteuert werden. Weiterhin enthält diese Karte die Hardware für den Port 78H, der für das Bankswitching verantwortlich ist. Über den Port 78H kann aber nicht nur das Ausblenden des MOS ROMs und des CRT RAMs gesteuert werden, sondern auch zwei zusätzliche 48K RAM Karten. Es stehen dann insgesamt 160K RAM in 3 Pages a 48K + 16K Common RAM zur Verfügung. Das schreit ja direkt nach einem Betriebssystem wie MP/M oder CP/M PLUS.

    Wie helwie44 weiter oben schon ausgeführt hat, sind dazu eine geeignete CPU und CRT Karte erforderlich, die das von der CAAC08 Karte erzeugte "Page0" Signal auswerten können.


    Viele Grüße

    netmercer

  • Wo hast du die ausgegraben?


    Ein Teil der Unterlagen von Haltenorth, die klaly gescannt hat:


    auf Bitte Verfasser gelöscht, kraus, 2021-11-12

    -------------------------------------------------------------------------------
    Suche Rechentechnik aus Deutschland, bzw. Computer Deutscher Hersteller - z.B.

    ANKER, AKKORD, CTM (CTM 70, CTM 9000, CTM 9032), DIEHL/ DDS, DIETZ, FEILER, ISE,
    HOHNER GDC, KIENZLE, KRANTZ, NIXDORF, OLYMPIA, PCS/CADMUS, RUF, SALOTA, S.E.I.,
    SIEMAG, SIEMENS, TAYLORIX, TRIUMPH ADLER - TA, WAGNER, WALTHER, WANDERER,...

    -------------------------------------------------------------------------------