Posts by jlopez

    Hello Helmut,


    Thank you for the schematics!


    As you know, I have hand-drawn a few ideas, and these days I'll try to find a state of harmony between them and the existing schematics. I don't plan to have a 128K board yet. However I won't stick to 64K. The third iteration will be a 66+6K (or 65+6K, I'll need to do some more research about). As 8 ICs per 18x10 cm is wasting the board, I'll focus to integrate a 6116 2K SRAM and a 2764 pin-compatible ROM. Most decode logic is already there, a few additions should be made to address those. However placing a ROM generates a new problem, as this component cares if their addresses or data are negated.


    The placement of the ROM came bacause I found that (as I already stated) most decode logic was already present and making a System ROM replacement board was a bad idea, as decode logic would be duplicate within the memory board and still it would have a low IC count. Considering both ideas brought me to modify the current board into a complete RAM-ROM replacement.


    Regards

    Greetings!


    I'm here again. I'll resume my work on this for a few days, but I'll need to be gone again some days before the exam... Still I think there's time enough to start redrawing the third iteration of the board. The second prototype of "mammooth" still needs to be ordered because as it was the first time and I didn't knew if I had enough time before the deadlines I prefered to do it after those events.

    Wow, that's a nice board!


    There aren't schematics but I think I have a vague idea of how it works.


    There are three bus transceivers. Two of them are '373 and the other one is a '245. I don't see anybody working with half address bus in positive logic and the other half in negative (it could be, but I don't see it) so let's assume he negated the full address bus to operate the memories with positive addresses and left the data negated.


    I imagine the '00 is wired in a similar way as my '02 and the result is fed to the '138 enable pin. The more RAM ICs on a circuit, more complex is to drive them, so the '138 was most probably added to the design for this reason. The select pins may be fed by A15, A14 and A13.


    The only thing that I cannot figure why was done is that 8 DIL switch and a '30 (that is a 8-input NAND gate)...


    Note that this analysis is made after a quick look at the board, don't know if it actually works this way, but that's how imagine it working. May be wrong. :S

    Hello,


    This morning I've read about the 128K expansion on the P30/40 computers. Is this memory "seen" by the 8085? If it is, wouldn't you know what port should I access? I assume that the backplane pinout for columns A and B doesn't differ when comparing P1/2-P3/4 models, but is worth asking if it does before sending the gerber to some manufacturer.


    Max. in two days I'll put this project to a short sleep. This semester is reaching its end and I still have work to do (I've to hand-copy lots of kanji!). When the work is done, I'll wait for the prototype PCBs to arrive (I'll try to order them before switching back to Japanese mode).


    Thank you very much!

    I've checked the specs and seems that from the P2 onwards all computers on this family have only 64K... The memory map seems the same... So the P3/P4 are only P2U with different case, detachable keyboard and better floppy drives/hard drive? It's strange that no memory upgrades were made. Also I heard that the P30/40 are P3/P4 with an extra 8088 card... Sounds interesting.

    Greetings!


    I'm preparing a small prototype batch. Wire-wrap was most probably the cause of failure and cutting thin tracks and soldering only a few wires is better than that monster. It's the right time to make a few corrections and additions. I'm doing the firs part (corrections), however you are not the first to state that it may work with improved models of the computer family. What the requirements for the P3/30/4/40 are (memory map, io ports, values to make it switch, etc.)?


    About the 32Kmode, it does not complicate it, I know were to cut the line. It may not be necessary and I doubt it will be ever used. However, I prefer giving the user the chance of choice. It's just like the ZX-81, it can have up to 32K internal ram, 16 internal or external or just the 1K or 2K of the original build. There are people who upgrade and people who doesn't. The ones who doesn't don't want because they want to be in touch with the original limitations the original computer specs had. Nostalgia is very a curious feeling... :)

    Greetings!


    Today I've finished wiring the 64K wire-wrapped prototype. Although I soldered the switch I left it non-functional as I saw it was simpler.



    However, the wire-wrap is a mess and I got lost between wires. At the end, I performed a test and this is all I could get.



    The memory was not recognized by the computer, so obviously something was wrong in that board. I think the problem was not design, as it is very simple. The main issue there is the amount of wires between both memories and the connector. It's hard to work at that area of the board, it is crowded. Although this test was a failure, I will continue development of the board, probably developing a more serious solution other than wire-wrap.

    Hello Helmut!


    That's the same document I used but unfortunately the diagram seems partially erased too... :(

    I'll try to check some combinations and see if some of them have sense.


    Thank you very much!

    Greetings!


    In December I got interested on the TMS9927 and tried to dive in its internals. I've got the datasheets for both it and its second source 5027. The block diagram on the TMS9927 isn't very useful, it shows nearly no logic between different blocks. However, the 5027 block diagram reveals some interesting interactions between blocks. Unfortunately, all I could get is a lo-res scan of the datasheet where a lot of lines are missing, logic symbols are unrecognizable on some cases and labels are blurry. That's better than nothing, but if someone could provide me this diagram with better quality I'd be very pleased.


    (The foresaid block diagram, partially hand-redrawn)


    Thank you very much!

    Hello,


    Five years ago my father and I found in a village of the province of Lleida (Catalonia) our first Alphatronic P2. Soon, problems regarding the power supply started to make an act of presence. The first day, the filter was blown. I can't remember exactly how much time passed but in a three months term the power supply was dead. In our case, the 5v module failed. As some of its components were popular only in West Germany we couldn't find direct replacement or information was missing so my father decided to innovate "a bit" and bypassed the +/-5V unit.


    The bypass adapter, the connector of the ATX can be seen over the left border of the floppy drive surface. The 5V unit is removed and contacts placed on thhe screws, which are used in the design to send power between both boards.


    Here connection to the P2 power supply can be seen with detail. Ground is common.



    A pair, random pictures showing the connector of the ATX power supply with the adapter connected.


    We use an old ATX power supply (those with a switch), but if there isn't any available a modern one (those with push button) can also be used. Prior to that we used one of those and if you do, remember that, in order to start it you need to connect the contact of the green wire in the main connector of the PSU with any ground contact on the came connector.


    This does not fix your power supply, but allows the computer to turn on. I consider it an emergency repair and should not be considered a proper solution. It is very helpful, however.

    Woah! That's a good acquisition! Have you tested it? If you have IFU you can connect to a 1084 monitor, it can only be seen in grayscale but at least is something. My unit has the RGB-mod pending. Now you have to get any CD-ROM2 drive to unleash all the potential of this machine. Also be cautious because they were rushed into the market and bad soldering points are very common.

    Hello Helmut, glad to see you here!


    In the 64K version of the board, the lower 16K are switched on/off by writing x1xxxxxx/x0xxxxxx at 78h (wired as 87h as the bus is negated). The switches only "cut" functionality of the circuit to ignore banking or decode logic. The lower 16K are disabled when reseted (or powered on) and can only be enabled by writing into the register if the switch allows it to.


    Apparently there are at least a pair of P1 units running free on the wild, excluding them is not an option for me. Sooner or later they will appear and require some help.


    I don't know how would this work with a computer other than the P1/P2 models. As the P1 is a cut-down version of the P2 is easy to see how to proceed, but the P3/P4/P30/P40 models are improved versions and unfortunately I have no units of these models to test any of my designs. However, if this can solve issues for all the range of the computers I'll be happier than if it only solves issues for the P2.


    The schematic previously posted is a preview, so it is unfinished and it may contain errors and need a pin rearrangement for the RAMs. Don't use it yet, please.


    Thank you very much!

    Welcome here! You did a very nice job!

    Thank you. :)


    I won't kept my word so I'm posting the first version of "Mammooth" schematics before its testing. It should be able to address 64K by writing at the register at 0x78. Two of the ICs are to protect the computer, my first aproaches with the switch was to drive directly the decode signal through them, but I realized that if someone accidentally modifies the switch with the computer powered and working there could be some problems, so I decided to put an extra '74 to store the position of the switch when it powers up. I'm wiring the prototype without this protective section, but if this design gives you enough confidence I could give up on that scary wire-wrap and order a batch for testing.


    P2 - Mammoth.pdf


    What do you think about it?

    Hello!


    In late November I bought my second P2 unit, an Italian one. Before it arrived, I started thinking about spare parts and how expensive and difficult to find are some of its components. So I started a project to replace any faulty memory board on any P1/P2. I called it "Elephant", as elephants have good memory. The goal is to produce new boards with new and lesser ICs (all of them modern, of course). At this point I have two designs: a minimalistic 3-ic design which provides 48KB called "pygmy" and the complete, switch-configurable to 32, 48 and 64Kb with 10 ics called "mammooth".


    Yesterday I finished soldering all wires on the "pygmy" prototype and tested it on the Italian unit. the full 48Kb memory was recognized and I could boot to CP/M with no problem at all. I am currently rewiring the prototype to turn it into an 8-ic 64Kb board.



    The wire-wrapped board, front side.



    The wire-wrapped board, back side.



    The prototype board attached into the bus.



    The prototype board, during testing. 4010-FFEF message returned after cold reset.


    P2_Elephant.pdf
    Here are the schematics for the "pygmy", which is the one tested. I'll post the next version once I have tested it.


    Once the second and final version is tested, I'm planning to design the board itself and place an order to manufacture them. I hope helps to extend the life of these computers a few more years.


    Thank you very much!