Thank you for the schematics!
As you know, I have hand-drawn a few ideas, and these days I'll try to find a state of harmony between them and the existing schematics. I don't plan to have a 128K board yet. However I won't stick to 64K. The third iteration will be a 66+6K (or 65+6K, I'll need to do some more research about). As 8 ICs per 18x10 cm is wasting the board, I'll focus to integrate a 6116 2K SRAM and a 2764 pin-compatible ROM. Most decode logic is already there, a few additions should be made to address those. However placing a ROM generates a new problem, as this component cares if their addresses or data are negated.
The placement of the ROM came bacause I found that (as I already stated) most decode logic was already present and making a System ROM replacement board was a bad idea, as decode logic would be duplicate within the memory board and still it would have a low IC count. Considering both ideas brought me to modify the current board into a complete RAM-ROM replacement.